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Verilog2001及SystemVerilog入門指引(第二版)

Verilog2001及SystemVerilog入門指引(第二版)

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訂購需時10-14天
9789864634323
具再熙
全華圖書
2016年12月29日
173.00  元
HK$ 164.35
省下 $8.65
 
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ISBN:9789864634323
  • 叢書系列:大專電子
  • 規格:平裝 / 522頁 / 20k
    大專電子


  • 專業/教科書/政府出版品 > 電機資訊類 > 電子











      電路設計小型化和系統化是未來的趨勢,傳統電路層級的設計已不能滿足複雜化和小型化的要求,新一代的SystemVerilog一經提出,便已受到廣大的關注,在短短的幾年內,便得到所有EDA大場的全力支持,而且也得到IEEE認可為新的標準,做為IC設計的第二大國,我們不能忽視這個潮流。藉由本書大量的範例,可增加演練的機會,相信一定能提升電路設計的能力。本書適用於大學、科大電子、電機、資工系「硬體描述語言」並且使用Verilog之課程使用。



    本書特色



      1.使用System Verilog程式語言

      2.內容詳細介紹System Verilog語法敘述,是不可缺少的工具書

      3.本書附上大量範例,讓讀者從實例中學習,且應用於系統當中

    ?





    第1章 overview

    發展歷史 1-1

    EDA工具的支持進度 1-3

    SystemVerilog的特性 1-3

    SystemC 1-11

    第2章 Verilog 2001

    回顧Verilog 2001 2-1

    Register changed to “variable” 2-4

    $ferror 2-68

    $fflush 2-69

    $fgetc 2-70

    $fgets 2-72

    $fread 2-74

    $fscanf 2-76

    $fseek 2-77

    第3章 Data Type

    資料型態 3-1

    auto variable vs static variable 3-1

    Constant 3-6

    Scope and lifetime 3-8

    Nets and regs 3-12

    State 3-16

    2-State data type 3-17

    logic data type 3-18

    Void data type 3-19

    String data type 3-20

    String operators 3-22

    String method 3-25

    Event data type 3-29

    User defined data type 3-30

    Enumerate data type 3-31

    Enumerated type ranges 3-34

    Enumerated types in numerical expressions 3-35

    Enumeration method 3-37

    Pack vs Unpacked 3-39

    Structures 3-40

    Packed Unpacked structures 3-45

    Packed Union 3-46

    Casting 3-50

    Dynamic casting 3-55

    Array 3-57

    Indexing and slicing of Array 3-59

    Array function 3-61

    Dynamic-array 3-63

    Associative-array 3-64

    Queue 3-67

    Queue function 3-70

    第4章 Operator

    Operator and expression 4-1

    Assignment operator 4-2

    Wildcard equality and inequality operators 4-7

    Uniary operator 4-12

    binary operator 4-13

    Static prefixes 4-16

    Concatenation 4-18

    Struct 4-20

    Set membership 4-22

    第5章 Procedural & Control

    Procedural & Control 5-1

    Selection statements 5-2

    Loop statements 5-3

    disable block 5-9

    name blocks 5-11

    return 5-12

    foreach 5-14

    final 5-15

    event control 5-16

    fork join fork join_none fork_join_any 5-21

    wait fork disable fork 5-25

    Synthesis convenient 5-25

    第6章 Tasks and functions

    Tasks and functions 6-1

    忽略begin end 6-4

    SystemVerilog function 6-5

    Pass by value 6-8

    Pass by reference 6-9

    Pass by name 6-12

    Self-defined data type task or functions 6-13

    第7章 Interface

    Interface 7-1

    Name bundle vs generic bundle 7-8

    Interface reference 7-11

    Ports in reference 7-11

    Modports 7-14

    Parameters 7-20

    第8章 Class

    OOP(Object Oriented Programming) 8-1

    class 8-2

    constructors 8-4

    object method 8-4

    assignment 8-11

    static class properties 8-13

    This 8-16

    inheritance 8-17

    overridden members 8-19

    super 8-20

    Data hiding local 8-21

    Data hiding protected 8-21

    virtual class 8-23

    第9章 Random Constraints

    Random Constraints 9-1

    randomize() with 9-4

    distribution 9-6

    function in constraints 9-7

    rand in class 9-8

    Inheritance 9-12

    Implication(->) 9-17

    Random weighted case(randcase) 9-22

    $urandom and $urandom_range 9-25

    rand_mode 9-27

    constraint_mode 9-27

    第10章 Coverage

    驗證Coverage 10-1

    覆蓋率Coverage 10-2

    Covergroup 10-4

    Coverpoints 10-5

    Coverage bins 10-8

    Cross coverage 10-15

    Covergroup guard 10-16

    Specify coverage options 10-18

    covergroup parameters 10-19

    ignore bins 10-21

    illegal bins 10-22

    第11章 Assertions

    Assertion verification 11-1

    Sequence declarations 11-3

    Uprange sign 11-4

    Implication Operators 11-10

    Consecutive repetition 11-11

    Non-consecutive repetition 11-13

    Goto repetition 11-15

    And operation 11-19

    OR operation 11-24

    Sample value function 11-28

    Condition over sequence 11-28

    Intersect operator 11-35

    first_match operator 11-40

    序列裏含匯流排資料 11-43

    Assertion 11-44

    Property 11-45

    附 錄

    A.1 SYNOPSYS VCS 附-1

    A.2.1 Cadence NC 附-3

    A.2.2 Running Coverage with Cadence Incisive 附-3

    A.2.3 Running Coverage with Cadence Incisive 附-4

    B.1 Source text 附-9

    B.1.1 Library source text 附-9

    B.1.2 Configuration source text 附-9

    B.1.3 Module and primitive source text 附-10

    B.1.4 Module parameters and ports 附-13

    B.1.5 Module items 附-14

    B.1.6 Interface items 附-17

    B.1.7 Program items 附-18

    B.1.8 Class items 附-18

    B.1.9 Constraints 附-20

    B.2 Declarations 附-21

    B.2.1 Declaration types 附-21

    B.2.2 Declaration data types 附-23

    B.2.3 Declaration lists 附-26

    B.2.4 Declaration assignments 附-27

    B.2.5 Declaration ranges 附-28

    B.2.6 Function declarations 附-28

    B.2.7 Task declarations 附-31

    B.2.8 Block item declarations 附-33

    B.2.9 Interface declarations 附-33

    B.2.10 Assertion declarations 附-34

    B.3 Primitive instances 附-38

    B.3.1 Primitive instantiation and instances 附-38

    B.3.2 Primitive strengths 附-39

    B.3.3 Primitive terminals 附-40

    B.3.4 Primitive gate and switch types 附-40

    B.4 Module, interface and generated instantiation 附-40

    B.4.1 Instantiation 附-40

    B.4.2 Generated instantiation 附-42

    B.5 UDP declaration and instantiation 附-44

    B.5.1 UDP declaration 附-44

    B.5.2 UDP ports 附-45

    B.5.3 UDP body 附-46

    B.5.4 UDP instantiation 附-47

    B.6 Behavioral statements 附-47

    B.6.1 Continuous assignment and net alias statements 附-47

    B.6.2 Procedural blocks and assignments 附-47

    B.6.3 Parallel and sequential blocks 附-49

    B.6.4 Statements 附-49

    B.6.5 Timing control statements 附-51

    B.6.7 Case statements 附-53

    B.6.8 Looping statements 附-54

    B.6.9 Task enable statements 附-55

    B.6.10 Assertion statements 附-55

    B.6.11 Clocking domain 附-55

    B.7 Specify section 附-57

    B.7.1 Specify block declaration 附-57

    B.7.2 Specify path declarations 附-57

    B.7.3 Specify block terminals 附-58

    B.7.4 Specify path delays 附-58

    B.7.5 System timing checks 附-60

    B.8 Expressions 附-64

    B.8.1 Concatenations 附-64

    B.8.2 Function calls 附-65

    B.8.3 Expressions 附-66

    B.8.4 Primaries 附-69

    B.8.5 Expression left-side values 附-71

    B.8.6 Operators 附-71

    B.8.7 Numbers 附-72

    B.8.8 Strings 附-73

    B.9 General 附-73

    B.9.1 Attributes 附-73

    B.9.2 Comments 附-74

    B.9.3 Identifiers 附-74

    B.9.4 Identifier branches 附-77

    B.9.5 White space 附-77




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