- 定價650.00元
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8
折優惠：HK$520
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DESIGN THROUGH VERILOG HDL
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沒有庫存
訂購需時10-14天
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9780471441489 | |
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PADMANABHAN、 SUNDARI? | |
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全華科技 | |
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2004年1月01日
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340.00 元
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HK$ 323
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詳
細
資
料
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* 規格：精裝 / 472頁 / 普級 / 單色印刷 / 初版
* 出版地：台灣
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類
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類
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推
薦
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內
容
簡
介
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Large and complicated digital circuits can beincorporated into hardware by using Verilog, a hardwaredescription language (HDL). A designer aspiring tomaster this versatile language must first becomefamiliar with its constructs, practice their use inreal applications, and apply them in combinations inorder to be successful. Design Through Verilog HDLaffords novices the opportunity to perform all of thesetasks, while also offering seasoned professionals acomprehensive resource on this dynamic tool.
本書特色
Each chapter concludes with exercises that both ensurereaders have mastered the present material andstimulate readers to explore avenues of their ownchoosing. Written and assembled in a paced, logicalmanner, Design Through Verilog HDL providesprofessionals, graduate students, and advancedundergraduates with a one-of-a-kind resource.
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目
錄
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Introduction to VLSI Design.
Introduction to VERILOG.
Language Constructs and Conventions in VERILOG.
Gate Level Modeling-1.
Gate Level Modeling-2.
Modeling at Data Flow Level.
Behavioral Modeling-1.
Behavioral Modeling-2.
Functions, Tasks, and User-Defined Primitives.
Switch Level Modeling.
System Tasks, Functions, and Compiler Directives.
Queues, PLAs, and FSMS.
Appendix A: Keywords and their Significance.
Appendix B: Truth Tables of Gates and Switches.
References.
Index.
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