- 定價127.00元
-
8
折優惠：HK$101.6
|
|
|
|
VHDL FOR ENGINEERS (PIE)
|
|
沒有庫存
訂購需時10-14天
|
|
|
|
|
|
9780135018101 | |
|
|
|
KENNETH L. SHORT | |
|
|
|
全華科技 | |
|
|
|
2009年1月01日
| |
|
|
|
367.00 元
| |
|
|
|
HK$ 348.65
|
|
|
|
|
| |
|
|
|
|
| |
|
|
詳
細
資
料
|
* 叢書系列：大專電子
* 規格：平裝 / 681頁 / 普級 / 單色印刷 / 初版
* 出版地：台灣
大專電子
|
|
分
類
|
專業/教科書/政府出版品 > 電機資訊類 > 電子 |
同
類
書
推
薦
|
|
|
內
容
簡
介
|
Suitable for use in a one- or two-semester course for computer and electrical engineering majors.VHDL for Engineers teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.
本書特色
1 . Logical Progression - Readers can begin producing synthesizable designs quickly because mastery of the VHDL language and usage progresses in step-wise fashion from simple to complex.
2 . Streamlined Coverage - VHDL constructs that are not useful for writing synthesizable design descriptions or testbenches are not covered in the text.
3 . Focus on Methodology - Design methodology and examples presented in the book are independent of any particular set of VHDL software tools or target PDL devices, to ensure that concepts are the focus. As a nonproprietary standard, VHDL designs are portable to other vendors’’ software tools and/or PLDs.
4 . Design Flow - Focus on the design flow in the VHDL/PLD design methodology is used in each step. Applied Learning - More then 275 block diagrams, logic diagrams, and timing waveforms and 180+ program listings illustrate the design concepts, cementing the VHDL/PLD design methodology.
5 . Professional Standards - Programming examples are compliant with the IEEE standard 1076-2002 for simulation and the IEEE standard 107
6 . 6-2004 for synthesis.
6 . Student Software - Aldec Active-HDL
7 . 2 Student Edition Software, an ideal design and simulation environment for learning VHDL, is packaged with each text. This text also establishes a useful starting point for VHDL- based application-specific integrated circuits (ASICs) design. Similar processes are used to synthesize and test PLDs and to synthesize and test ASICs.
|
|
目
錄
|
Preface
1 Di g i t a l Design Using VHDL and PLDs 1
2 E n t it i e s , Archi t e ct u r e s , and Cod ing S t y les 44
3 Signals and Data Types 82
4 Dataf low Style Combinational Design 123
5 Behavi o r a l S t y le Combinational Design 165
6 Event-Dr i v en Simulation 201
7 Testbenche s for Combinational Designs 251
8 Latches and F l i p - f l ops 304
9 Multibi t L a t ches, Regist e r s , Count e r s , and Memory 337
10 F i n i te State Machines 380
11 ASM Charts and RTL Des i gn 431
12 Subprograms 469
13 Packages 501
14 Testbenches for S equent i a l S y s tems 526
15 Modular Des ign and Hie rarchy 566
16 More Des ign Examples 615
Appendix VHDL At t r i b u t e s 659
Bibliography 663
Index
|
|
|
書
評
|
|
|
|
|
